Microwave Engineering Project

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Heads-up Display Proposal for GNU Radio (and MEP)

Six-Ports

Paper appearing in The Proceedings of Microwave Update 2011. It's about the basics of six-port theory, with an explanation of six-ports as modulator and demodulator.

Six-port article for MUD

Greetings all! This October, a six-port paper will be included in the Proceedings of Microwave Update 2011. If you read the old six-port paper, this is a major revision and expansion.  http://www.delmarnorth.com/microwave/newsletters/sixportmodel.pdf Next step: building six-ports with the recently received couplers and dividers, at 1.2GHz in order to experiment with local amateur DTV.  https://plus.google.com/114254220048556407553/posts/MVTkLTbNuXB I'm hoping that experiments at 1.2GH...

Qt4 built, building a GUI for SDRs

After reinstalling Xcode, Qt4 installed from the repository. This is the recommended way to build GUIs for MEP. Thanks to Jacob for highlighting Qt4 and recommending a book. If you're interested in building the GUI, then install Qt and speak up!  :+) Tom Rondeau had some very nice things to say about a model-view-controller architecture-for-SDR letter I wrote him and fred harris a couple months back. The response got me thinking about exactly how one would want to partition tasks for an S...

Numbering Scheme, looking for hybrid couplers and dividers, and MUD?

Hi everyone!  Here's a document about the numbering scheme in the IQ Gain and Phase Correction Filter.  I bought the first set of parts for experimenting with six-port structures. Two 90 degree hybrid couplers off eBay. The target application is DVB amateur television. There's a repeater near me for DVB ATV. The frequency of interest for this experiment is 1.2GHz. If you have any 90 degree hybrid couplers or power dividers for this frequency, and are willing to donate them to the cause, ...

FPGAs in space

Article from EE Times about FPGAs in a cubesat project. http://www.eetimes.com/design/military-aerospace-design/4216480/High-performance-FPGAs-take-flight-in-microsatellites?cid=NL_ProgrammableLogic&Ecosystem=programmable-logic  -Michelle W5NYV Potestatem obscuri lateris nescis.

VHDL implementation compared to MATLAB model - overall success

Overview of successful results with synthesizeable VHDL implementation. Comparison with MATLAB results. -Michelle W5NYV

"What's Up With ARM"

Here's an opinion piece about the current state of Linux development on ARM. I thought it was interesting, largely agree with the author, and wanted to share it with you guys. http://www.linux.com/news/featured-blogs/171-jonathan-corbet/445344-whats-up-with-arm Having got the beagleboard lab back up and running after the extended tour of duty doing VHDL, I find that it is very true that getting Linux working on ARM can be much more "some assembly required" than, say, a desktop. It's well...

updated synthesizeable VHDL block - progress

Here is updated VHDL code for the IQ Gain and Phase Correction filter. I'm working with an adjusted numbering scheme in signed arithmetic to correct an overflow problem (thanks to KB5MU, who helped identify).  This implementation, which is designed to be synthesizeable, is beginning to function as intended. There is a factor of two error, but the compiled block outputs I and Q. With some data visualization, these might prove to be a passed-through I and phase corrected Q at the output,...

VHDL update - IQ Gain and Phase correction, next blocks

Hi everyone! I'm back to work on the VHDL after an interruption for a DXpedition to Curaçao, spring break shennanigans, and photographing a wedding. I took the entity, architecture, and the testbench from the variable (non-synthesizeable) version, and started a new workspace. The goal is to get the register-based version working. When last I attempted this, I got incorrect results from multiplication. I'm making another run at it to get this filter ready for synthesis (when it's put int...

IQ Correction VHDL update

Greetings everyone, I have a VHDL implementation of the IQ phase and gain correction algorithm working. This implementation isn't synthesizeable in logic (yet), but it will be as soon as I figure out why signed multiplication gives the wrong result. Since I have a version that is working (with some of the internal math done with variables instead of registers) I'm taking the opportunity to work on gain and phase lock and the creation of "corrected" I and Q signals. I is passed along wit...

Package that makes normally distributed random numbers from uniform numbers

In order to be able to have normal distribution noise, I made a package that takes the uniform distribution random numbers and uses the central limit theorem to give an (approximately) normal distribution. Here's the package: library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use work.random_int.all; --by MEP 22 February 2011 --usage: --this is a function, which means it can be on the right-hand side --of an assignment. It returns a mean-zero ran...

Package that creates I and Q samples to test the IQ Correction block

library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use work.normal_distribution_random_noise.all; --by MEP 22 February 2011 --usage: --these are functions, which means they can be on the right-hand side --of an assignment. These functions create an I and Q sample. --The arguments are --a natural number standing for the index of the sample, --a real number that provides a way to have many samples per period, --a real number standing for the standard d...

IQ Phase Gain Correction testbench

library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use work.normal_distribution_random_noise.all; use work.create_sample.all; entity IQGainPhaseCorrection_testbench is end entity; architecture IQGainPhaseCorrection_testbench_arch of IQGainPhaseCorrection_testbench is --declare the DUT as a component. component IQGainPhaseCorrection is generic(width :natural); port( clk :in std_logic; x1 :in signed(width...

IQ Phase Gain Correction entity

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith; use ieee.numeric_std.all; entity IQGainPhaseCorrection is generic(width:natural); port( clk :in std_logic; x1 :in signed(width downto 0); y1 :in signed(width downto 0); gain_error :out signed(width downto 0); gain_lock :out bit; phase_error :out signed(width downto 0); phase_lock :out bit; corrected_x1 :out signed...

IQ Phase Gain Correction architecture

architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is --signal declarations --phase error estimate accumulator signal reg_1:signed(width downto 0) := (others => '0'); --gain error estimate accumulator signal reg_2:signed(width downto 0) := (0 => '1', others => '0'); --Phase Offset Adjustment Applied to y1 signal y2:signed(width downto 0) := (others => '0'); --Gain and Phase Adjustment Applied to y1 signal y3:signed(2*width+1 downto 0...

IQ Phase and Gain Correction - Testbench

Below is the testbench for the IQ Phase and Gain Correction. As you can see, there's a lot more going on in the testbench than in the block for the algorithm. This is because the testbench has to generate the test signals and provide the clock and establish the various settings for the test, and that all adds up in this case to more lines of code. On the list of improvements is to move the I and Q signal creation into a procedure. This encapsulates code and will make the testbench a lo...

IQ Phase and Gain Correction

I'm working on the IQ Phase and Gain Correction VHDL implementation today. Here is the entity and architecture below. In the testbench, the phase correction works (with some amount of oscillation), but the gain correction increases without bound. Trying to track that down today. I'll post the testbench next in a separate email. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith; use ieee.numeric_std.all; entity IQGainPhaseCorrection is generic(width:natural); port( ...

VHDL experience so far

I'm halfway through the VHDL class and well into implementing the IQ Phase and Gain correction algorithm. I'll publish a cut of it in a separate email. What I wanted to share was a few very brief observations about learning VHDL. The actual description of what you want to accomplish may take much less time than constructing a test that really tests what you have designed. VHDL projects are usually broken down into components, which are the blocks that implement your function, and testben...

Software-defined radio ideas

From twitter this past week, Tom Rondeau asked: "I'm giving a day-long lecture on SDR. What would you want to hear about? I'm focusing on software and processing." Tom Rondeau is giving a talk with fred harris, a well-known DSP lecturer and professor at SDSU. Balister offered, "Explain the difference between a collection of functions that do operations and a framework providing structure for using them." What do you all think? What are the current concerns in software-defined radio de...

Pressing on with IQ Correction algorithm - vhdl entity and architecture update

Here's tonight's progress on the entity and architecture for the implementation of the IQ Correction algorithm. It compiled after solving some trouble I had with implmenting shifts. Standard logic vectors can't be shifted, but signed vectors can be. So converting, then shifting, then converting back did the trick. More soon, -Michelle W5NYV library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_signed.all; use ieee.numeric_std.all; entity IQGainPhaseCorrection is gene...

IQ Correction Model - proposed plotting change, question about absolute values

PDF attached. More soon! -Michelle W5NYV

IQ Correct entity and architecture files - update

Here's the snapshot of the latest work on the entity and architecture for the IQ gain and phase correction algorithm. more soon! -Michelle W5NYV

IQ Correction entity, architecture update

entity IQGainPhaseCorrection is generic(input_width:natural:=12; output_width:natural:=7); port( clk:in bit; x1:in bit_vector(input_width downto 0); y1:in bit_vector(input_width downto 0); gain_error:out bit_vector(output_width downto 0); phase_error:out bit_vector(output_width downto 0) ); end IQGainPhaseCorrection; architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is begin --as long as there are samples, do a loop correction : process is --local variables v...